Browse Prior Art Database

Automated Chip Array Testing

IP.com Disclosure Number: IPCOM000038604D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Harrison, BR: AUTHOR [+3]

Abstract

In semiconductor gate arrays, designs complying with scan design rules, such as Level Sensitive Scan Design (LSSD), can be tested with automatically generated test patterns whereas non-LSSD designs require manually generated test patterns. When a mixture of LSSD and non-LSSD is required, non-LSSD portions may be isolated during automatic generation of test patterns. The technique reduces the number of manually generated test patterns required. In many gate array designs, cell count is often a significant constraint. Such designs may contain arrays of registers (such as register files, FIFOs, etc) comprising many latches all controlled by common, combinatorial logic, consuming large numbers of the cells available.

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Automated Chip Array Testing

In semiconductor gate arrays, designs complying with scan design rules, such as Level Sensitive Scan Design (LSSD), can be tested with automatically generated test patterns whereas non-LSSD designs require manually generated test patterns. When a mixture of LSSD and non-LSSD is required, non-LSSD portions may be isolated during automatic generation of test patterns. The technique reduces the number of manually generated test patterns required. In many gate array designs, cell count is often a significant constraint. Such designs may contain arrays of registers (such as register files, FIFOs, etc) comprising many latches all controlled by common, combinatorial logic, consuming large numbers of the cells available. Latches which comply with scan design rules, such as LSSD rules, frequently use more cells than their non-LSSD equivalents, and so the designer is often forced to produce such arrays using non-LSSD latches. To comply with the design rules, these non-LSSD elements must be logically isolated from the LSSD part of the design (as shown in Fig. 1) in order that the algorithmic (or automatic) test pattern generation (TPG) may be used to produce patterns to test the LSSD areas. However, as some of the inputs to the LSSD logic (item 3 in Fig. 1) are controlled by the isolated (and hence inactivated) outputs from the non- LSSD logic (item 2), the automatic TPG will be unable to fully test some elements in 3. The designer must then res...