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Manufacturing Process and Test Method for Masterslices With Non-Personalized First Metal Masks

IP.com Disclosure Number: IPCOM000038629D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Pollmann, K: AUTHOR [+4]

Abstract

For reducing the manufacturing time of integrated semiconductor circuits, it is proposed that the mask for the first metallization plane not be personalized. For this purpose, the following approach is used. 1) The transistors are wired to the logic basic function, say, a 2 W NAND circuit. Output 0 is wired to input I of the next basic function. 2) The wiring channels of the first metallization plane are filled with long lines 1 (Fig. 2). In edge areas 2 (Fig. 1), they are connected in the form of a meander. Edge areas 2 comprise underpasses 3 in the silicon material which permit all lines to be tested for interruptions and adjacent lines to be tested for shorts.

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Manufacturing Process and Test Method for Masterslices With Non- Personalized First Metal Masks

For reducing the manufacturing time of integrated semiconductor circuits, it is proposed that the mask for the first metallization plane not be personalized. For this purpose, the following approach is used. 1) The transistors are wired to the logic basic function, say, a 2 W NAND circuit. Output 0 is

wired to input I of the next basic function. 2) The wiring channels of the first metallization plane are filled with long lines 1

(Fig. 2). In edge areas 2 (Fig. 1), they are

connected in the form of a meander. Edge areas 2

comprise underpasses 3 in the silicon material

which permit all lines to be tested for

interruptions and adjacent lines to be tested for

shorts. 3) Several circuit rows have their wiring

connected, forming a ring oscillator which in kerf

area 4 is linked to test pads. 4) In addition to the usual connecting vias 6, the via mask (Fig. 2) is provided with etch vias 7

at points where a line is to be interrupted. The

personalized first metallization plane is obtained

by interrupting lines which were previously

functionally tested along with the transistors. 5) A block-out mask determines the vias 7 from which the first metallization plane is to be

etched. The accuracy of the dimensions is a

function of the via mask. Inaccurate edge areas

and the connection in the kerf area are removed by

etching. What remains is a personalized first metallization plane, the accuracy of whose dimensions is determined by the testable non-personalized plane. The yield after...