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Contactless Powering for Chip Testing

IP.com Disclosure Number: IPCOM000038630D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Beha, H: AUTHOR [+3]

Abstract

The rapid development of VLSI (very large-scale integration) and VHSIC (very high-speed integrated circuit) technology and design, which led to higher complexity, submicron size and very short switching times (10 - 20 ps), necessitates contactless testing techniques, as already proposed in the literature. Contactless testing is also absolutely essential for the internal chip or wafer nodes which are inaccessible through I/O pads. The chips must also be tested during their manufacture, i.e., before the I/O pads are produced. For this purpose, the chips are powered through mechanical needles whose size is limited to 1 to 2 mm, as the pad level is deposited in a later process step and the interconnections have to be contacted directly. Powering becomes problematic as the size of the integrated circuits decreases below 1 mm.

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Contactless Powering for Chip Testing

The rapid development of VLSI (very large-scale integration) and VHSIC (very high-speed integrated circuit) technology and design, which led to higher complexity, submicron size and very short switching times (10 - 20 ps), necessitates contactless testing techniques, as already proposed in the literature. Contactless testing is also absolutely essential for the internal chip or wafer nodes which are inaccessible through I/O pads. The chips must also be tested during their manufacture, i.e., before the I/O pads are produced. For this purpose, the chips are powered through mechanical needles whose size is limited to 1 to 2 mm, as the pad level is deposited in a later process step and the interconnections have to be contacted directly. Powering becomes problematic as the size of the integrated circuits decreases below 1 mm. In addition, it becomes increasingly difficult to position the mechanical needles without destroying the circuits on the chips or wafers. The contactless IC powering scheme described in this article comprises a planar diode array positioned on the wafer, as illustrated in the figure. The power is fed to the wafer through an optical beam which illuminates the diode array. The diodes convert the incoming optical power into electrical power of the desired voltage. The power is then distributed via a power bus to the individual wafer circuits. The circuits are subjected to contactless testing. Node voltages and c...