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Error Correction Circuit With Replacement Memory

IP.com Disclosure Number: IPCOM000038632D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Schmidt, M: AUTHOR [+2]

Abstract

As a storage location with several hard failures cannot be used, it is known to use a replacement location instead. In a directory, the addresses of all faulty storage locations are stored, and the storage address applied to the memory is compared with all addresses contained in the directory. In response to a compare on equal result, the replacement location is used. The directory is generally implemented as an associative memory and is therefore expensive. This article relates to the correction of more than one error in a data word by means of a replacement memory, without using a directory. It is suggested that a pointer, rather than a data word, be stored in a faulty location. The pointer is the address of the wanted data word in the replacement memory.

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Error Correction Circuit With Replacement Memory

As a storage location with several hard failures cannot be used, it is known to use a replacement location instead. In a directory, the addresses of all faulty storage locations are stored, and the storage address applied to the memory is compared with all addresses contained in the directory. In response to a compare on equal result, the replacement location is used. The directory is generally implemented as an associative memory and is therefore expensive. This article relates to the correction of more than one error in a data word by means of a replacement memory, without using a directory. It is suggested that a pointer, rather than a data word, be stored in a faulty location. The pointer is the address of the wanted data word in the replacement memory. To determine whether an addressed storage location contains a data word or a pointer, a special ECC (Error Correction Circuit) code is used. Referring to the device illustrated in the figure, the usual registers and buses in an information memory are shown. The storage address, stored in the address-in register, is applied to main storage MS1, and the contents of the addressed storage location are read into the data-out register from where they are transferred to the ECC decoder. When no error NE is detected, the read data are transferred to the processor. When a single error SE is detected, it is corrected by the ECC apparatus according to known methods. A double error DE may have two possible reasons: the addressed data word contains a double soft error or a pointer is stored in the addressed location. For ECC coding the data words and the pointer, a special BCH code is used. Code fo...