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Redundancy Scheme

IP.com Disclosure Number: IPCOM000038635D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Loehlein, WD: AUTHOR [+2]

Abstract

A redundancy scheme and a new circuit design are described which comprise an enhanced yield memory with no loss of access time. The figure shows in particular a new address true-complement (T/C) switch which provides the memory with a distinctive feature so that a thin-oxide capacitance during the normal operation of the memory passes unnoticed by the address inputs. There is no extra fuse, and thus no increase in DC power and time resulting from fuse blowing. If the chip is an all-good one, no redundant word or bit line WL or BL is required. Hence, there is no need to blow a fuse. Node C remains high to keep signal DSEL from staying low when signal ASW is activated. Transistors T17 and T18 are kept off by nodes E and F, so that address input A1C is isolated from the thin-oxide capacitance.

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Redundancy Scheme

A redundancy scheme and a new circuit design are described which comprise an enhanced yield memory with no loss of access time. The figure shows in particular a new address true-complement (T/C) switch which provides the memory with a distinctive feature so that a thin-oxide capacitance during the normal operation of the memory passes unnoticed by the address inputs. There is no extra fuse, and thus no increase in DC power and time resulting from fuse blowing. If the chip is an all-good one, no redundant word or bit line WL or BL is required. Hence, there is no need to blow a fuse. Node C remains high to keep signal DSEL from staying low when signal ASW is activated. Transistors T17 and T18 are kept off by nodes E and F, so that address input A1C is isolated from the thin-oxide capacitance. Similarly, transistors T15 and T16 are off, isolating input A1T from the thin-oxide capacitance, because nodes G and H are kept high and low, respectively, by nodes D and C and transistors T22, T23, T24 and T25. Thus, there are no yield losses attributable to downloading the address inputs. If a redundant word or bit line is needed, a fuse will be blown. Assuming the main fuse for nodes D and C is blown, then node C will be grounded, while node D is high. Transistor T1A is disabled, so that signal DSEL will remain low when the bad address is matched. For every address associated with the redundant word or bit line, fuse R1 will either be blown or be left inta...