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Noise-Tolerant Select Scheme for a Semiconductor Memory

IP.com Disclosure Number: IPCOM000038637D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Gepraegs, W: AUTHOR [+4]

Abstract

A circuit is described which prevents undesired noise spikes from selecting a memory array without the disadvantage of having to desensitize the input stages of the array, which would lead to considerable delays in access time. This is avoided by the present circuit which comprises at its input a fast inverter T1/T2, whose threshold is very close to its unselected state. As a result, the inverter responds at a very early stage, causing single-shot output C to be pulled to ground. The circuit output thus remains at its upper voltage level. At the end of the short pulse time of the single-shot, node C of the latter is raised to voltage VH, while the output of the illustrated circuit remains in the unselected state, as the noise spike has since disappeared and gate T12/T8 is grounded.

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Noise-Tolerant Select Scheme for a Semiconductor Memory

A circuit is described which prevents undesired noise spikes from selecting a memory array without the disadvantage of having to desensitize the input stages of the array, which would lead to considerable delays in access time. This is avoided by the present circuit which comprises at its input a fast inverter T1/T2, whose threshold is very close to its unselected state. As a result, the inverter responds at a very early stage, causing single-shot output C to be pulled to ground. The circuit output thus remains at its upper voltage level. At the end of the short pulse time of the single-shot, node C of the latter is raised to voltage VH, while the output of the illustrated circuit remains in the unselected state, as the noise spike has since disappeared and gate T12/T8 is grounded. In comparison with this, node A is charged to voltage VH during normal selection after the short pulse time, so that the output goes to ground level, initiating in the memory the internal chip-selection step. The timing diagram shows quite clearly that in response to a noise spike at the end of the single-shot time, the array select signal resumes its unselected state, so that there is no selection. As certain functions are already possible during the array selection fall time, the measures described reduce the delay in array selection (also, see the timing diagram).

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