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CECL With Multiple Current Paths

IP.com Disclosure Number: IPCOM000038647D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

The CECL (cascode emitter coupled logic) network described in this article can be used to increase the density of more complicated logic functions, in gate arrays or custom designs. In the conventional CECL gate shown in Fig. 1, one current path always exists in the logic tree, which reaches one of the two logic tree tops. Two CECL trees are thus needed in the conventional full (Image Omitted) adder in CECL trees of three cascode levels, as illustrated by Fig. 2. For higher density, however, the CECL tree can be so designed that one or more current paths may reach one of the multiple logic tree tops. A logic tree design is here disclosed in which one or more current paths may reach one or more of the logic tree tops.

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CECL With Multiple Current Paths

The CECL (cascode emitter coupled logic) network described in this article can be used to increase the density of more complicated logic functions, in gate arrays or custom designs. In the conventional CECL gate shown in Fig. 1, one current path always exists in the logic tree, which reaches one of the two logic tree tops. Two CECL trees are thus needed in the conventional full

(Image Omitted)

adder in CECL trees of three cascode levels, as illustrated by Fig. 2. For higher density, however, the CECL tree can be so designed that one or more current paths may reach one of the multiple logic tree tops. A logic tree design is here disclosed in which one or more current paths may reach one or more of the logic tree tops. While the currents through the individual current paths are no longer constant, with the output down level voltage clamped to Vcc-Vd the logic swings are always about the same. An implementation of a full adder with this CECL tree is shown in Fig. 3. In this implementation, transistors T1 and T2 may be on at the same time. Since they are identical transistors with the same Vbe, I1 N I2 N I/2. Thus when an output node is pulled down, the pull down current may be either I or I/2. However, the output down level is always N Vcc-Vd so long as I*R/2 > Vd. In general, the design rule for the CECL tree with multiple current paths is I*R/N > Vd, where I is the total current, R is the

load resistor, N is the maximum number

of

s...