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Failing Computer Memory Address Recapture and Dynamic Memory Refresh During Execution of Infinite Addressing

IP.com Disclosure Number: IPCOM000038658D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Sotolongo, H: AUTHOR

Abstract

A technique is described whereby the addresses of failed computer memory registers, involving correctable and uncorrectable multiple errors, are recaptured during error correcting operations. Also described is a memory refresh concept for handling dynamic memory refreshing when operations of infinite duration are encountered. Computer systems often utilize storage control units (SCUs) to control the memory addressing function of the system, such as reading and writing from and to storage, refreshing the dynamic memory chips, implementing error correcting codes (ECCs), etc.

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Failing Computer Memory Address Recapture and Dynamic Memory Refresh During Execution of Infinite Addressing

A technique is described whereby the addresses of failed computer memory registers, involving correctable and uncorrectable multiple errors, are recaptured during error correcting operations. Also described is a memory refresh concept for handling dynamic memory refreshing when operations of infinite duration are encountered. Computer systems often utilize storage control units (SCUs) to control the memory addressing function of the system, such as reading and writing from and to storage, refreshing the dynamic memory chips, implementing error correcting codes (ECCs), etc. A register called the failing storage address register (FSAR) is used to capture the address of a storage location where an ECC error occurred so that this register can later be read by means of interrupt handling software to identify the location of the problem. The concept described herein addresses the problem where multiple errors occur before the software reads the register. The algorithm used is as follows: The address of the location containing an ECC error will be captured and retained in the FSAR, unless the error is of the correctable type, and is followed by an uncorrectable error before the register is read. For this case, the address for the uncorrectable error over- writes the previous error and is retained until read by software. An uncorrectable error is a hardware failure from which the system may not recover. It may recover if on a retry, the error is not detected; then it is referred to as a soft error. A correctable error enables the system operation to continue, but at reduced performance when reading the address location encountering the error. Therefore, the address for the uncorrectable error should take precedence over that of the correctable type. The algorithm implemented in this concept maintains status bits indicating the type of error detected. The clock in the FSAR is controlled such that it will free run until an ECC error is detected. If the detected error on the FSAR is of the correctable type, the clock on the FSAR will be frozen, capturing the address of the error, and the correctable ECC error status will be set. If an uncorrectable error occurs, the clock of the FSAR will be gated ON for one cycle, using the status bit for the correctable error and the uncorrectable error indication to enable capturing the new address, which is still valid in the SCU. The uncorrectable error status will then be set. Thereafter, the uncorrectable error status indication will inhibit any further clocks in the FSAR until the register is read by software. The algorithm for the FSAR clock control latch is as follows: where: E1 = The first ECC storage error. E2 =...