Browse Prior Art Database

PC Board Construction Method

IP.com Disclosure Number: IPCOM000038710D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Hermann, K: AUTHOR [+2]

Abstract

This method provides for the construction of a thin multilayer printed circuit (PC) board. Typical process steps for the method of making a signal core of the board are as follows: (1) A sheet 1, e.g., 2-ounce cold rolled copper, is drilled or punched to form clearance holes 2 and 3 for subsequently formed plated-through holes (PTHs) and wiring vias, i.e., programmed vias (PVs), respectively (Fig. 1). (Image Omitted) (2) Appropriate thicknesses of epoxy-glass layers 4 are laminated on both surfaces of sheet 1. A layer 5 of sacrificial copper is provided on each of the outer surfaces of the layers 4 which roughen the epoxy of the outer surfaces for the subsequent sputter seed/lift-off process (Fig. 2).

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PC Board Construction Method

This method provides for the construction of a thin multilayer printed circuit (PC) board. Typical process steps for the method of making a signal core of the board are as follows: (1) A sheet 1, e.g., 2-ounce cold rolled copper, is drilled or punched to form clearance holes 2

and 3 for subsequently formed plated-through holes

(PTHs) and wiring vias, i.e., programmed vias

(PVs), respectively (Fig. 1).

(Image Omitted)

(2) Appropriate thicknesses of

epoxy-glass layers 4 are laminated on both

surfaces of sheet 1. A layer 5 of sacrificial

copper is provided on each of the outer surfaces

of the layers 4 which roughen the epoxy of the

outer surfaces for the subsequent sputter

seed/lift-off process (Fig. 2). (3) Openings through the layers 4 and 5 to the programmed vias, e.g., PV 3, are provided by

mechanically drilling or, alternatively, by using

dot etch or laser drill techniques (Fig. 3). (4) The sacrificial copper layers 5 are then removed by etching (Fig. 4). (5) A photosensitive dielectric (PSD) film 6 (or conventional film photoresist which would be later

stripped) is then laminated on each side of the

structure (Fig. 5) and is exposed and developed. (6) After sputter seeding, lift-off and electroless additive plating, the resultant signal

core structure of Fig. 6 is provided with the

plating 7 and signal conductors 8, and the PSD

layer 6 is thereafter removed. If peel-apart

copper (PAP) or 1/2-ounce copper is used for the

layers 5, the signal cores could be

electro-pattern plated. (7) Fig. 7 shows a six-signal plane (S1 - S6) composite structure of three signal core

structures, each made by the afore-described

method. Optionally, reference planes REF 1

and 5 may be omitted and...