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High-Performance Lateral PNP Transistor Structure

IP.com Disclosure Number: IPCOM000038714D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Jan-31
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR

Abstract

The lateral PNP transistor structure described uses a concentric ring- type geometry with a minimized emitter area and with a minimum detrimental effect of the parasitic diode which exists under the emitter. The result is improved gain and frequency response compared to conventional lateral PNP devices. Fig. 1 shows a plan view of the structure, including the top level metal connections, and Fig. 2 shows a cross-section which does not include the metal connections. Metal pattern 1 connects to the base, metal pattern 2 is the emitter connection, and metal pattern 3 connects to the collector regions. (Image Omitted) Region 4 is an N+ diffusion which makes the connection to the N- region 5 which is used for the transistor base. Regions 6 and 7 are P diffusions which are part of a "ring" which forms a collector.

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High-Performance Lateral PNP Transistor Structure

The lateral PNP transistor structure described uses a concentric ring- type geometry with a minimized emitter area and with a minimum detrimental effect of the parasitic diode which exists under the emitter. The result is improved gain and frequency response compared to conventional lateral PNP devices. Fig. 1 shows a plan view of the structure, including the top level metal connections, and Fig. 2 shows a cross-section which does not include the metal connections. Metal pattern 1 connects to the base, metal pattern 2 is the emitter connection, and metal pattern 3 connects to the collector regions.

(Image Omitted)

Region 4 is an N+ diffusion which makes the connection to the N- region 5 which is used for the transistor base. Regions 6 and 7 are P diffusions which are part of a "ring" which forms a collector. Similarly, regions 8 and 9 are P+ diffusions which are part of a ring which forms an emitter. Region 10 is a P+ diffusion "island" forming another collector area. The process used to form the P+ diffusions, including the collector and emitter rings and the collector island, uses the same mask. The self-alignment permits achieving small dimensions of the patterns for high performance. The structure can be visualized as two transistors in parallel, with one being formed by the outer collector ring, the substrate being the base region, and the emitter ring. The other is the inner collector island region 10, the s...