Browse Prior Art Database

Oscillator Switching Circuit

IP.com Disclosure Number: IPCOM000038742D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Dougal, GM: AUTHOR [+2]

Abstract

In a display system where screen size is selectable, changing screen size requires changing oscillator frequency controlling clocks for Level Sensitive Scan Design (LSSD) logic. This change can cause glitch problems which are avoided by using an asynchronous pulse from the controlling processor during the frequency change. As shown in Figs. 1 and 2, a clock splitter runs from one of two oscillators OLD OSC and NEW OSC, and generates non-overlapping LSSD clocks FASTC and FASTB. When modes are changed, i.e., oscillator frequencies switched, spurious clock pulses can be obtained (the worst two cases being shown in Figs. 1 and 2). If a mode register controls this switching and it is clocked by FASTC and FASTB (i.e.

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Oscillator Switching Circuit

In a display system where screen size is selectable, changing screen size requires changing oscillator frequency controlling clocks for Level Sensitive Scan Design (LSSD) logic. This change can cause glitch problems which are avoided by using an asynchronous pulse from the controlling processor during the frequency change. As shown in Figs. 1 and 2, a clock splitter runs from one of two oscillators OLD OSC and NEW OSC, and generates non-overlapping LSSD clocks FASTC and FASTB. When modes are changed, i.e., oscillator frequencies switched, spurious clock pulses can be obtained (the worst two cases being shown in Figs. 1 and 2). If a mode register controls this switching and it is clocked by FASTC and FASTB (i.e., it is a normal L1, L2 LSSD SRL), the spurious clock pulses can corrupt the contents of the register by clocking after the data is no longer valid. This induces a further oscillator switch, thus selecting the wrong oscillator, or no oscillator at all. This problem is overcome as follows and as shown in Fig. 3. The L1, L2 SRL is implemented as normal for scanning in test. In function, however, the L1 is clocked by an asynchronous write pulse, of the correct address, and the L2 is held open.

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As a result of this structure, the spurious pulses on FASTC and FASTB can in fact be made worse, due to the random early data from the PC appearing on the select line. However as the oscillator select register or mode register...