Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Method for Addressing a Two-Dimensional Memory With Address Incrementing Random-Access Memories

IP.com Disclosure Number: IPCOM000038744D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Burroughs, SH: AUTHOR [+3]

Abstract

A method is described which allows a significant reduction in the complexity of the Dynamic Random-Access Memory (DRAM) addressing circuitry. A method for accessing a two-dimensional memory array in either the horizontal or vertical direction without regard to byte or word boundaries is ******** in the prior art. In that arrangement, memory modules are arranged in the array on a diagonal so that all modules are accessed, each cycle independent of direction of access. An implementation of this addressing method with conventional DRAMs is shown in Fig. 1. In this example, 16 64Kx1 DRAMs are used to create a 1024 x 1024-bit map. A 10-bit X address and a 10-bit Y address are processed by the addressing circuitry to create 16 8-bit row/column addresses.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 60% of the total text.

Page 1 of 2

Method for Addressing a Two-Dimensional Memory With Address Incrementing Random-Access Memories

A method is described which allows a significant reduction in the complexity of the Dynamic Random-Access Memory (DRAM) addressing circuitry. A method for accessing a two-dimensional memory array in either the horizontal or vertical direction without regard to byte or word boundaries is ******** in the prior art. In that arrangement, memory modules are arranged in the array on a diagonal so that all modules are accessed, each cycle independent of direction of access.

An implementation of this addressing method with conventional DRAMs is shown in Fig. 1. In this example, 16 64Kx1 DRAMs are used to create a 1024 x 1024-bit map. A 10-bit X address and a 10-bit Y address are processed by the addressing circuitry to create 16 8-bit row/column addresses.

(Image Omitted)

The mapping from 10-bit X and Y addresses to 8-bit row and column addresses is shown in Fig. 2. In this addressing scheme, the column address is incremented with every 16 counts across in X while the row address is incremented with every 4 counts down in Y. An Address Incrementing DRAM (AIDRAM) is a 64Kx1 DRAM with an extra pin called "address increment." When this pin is activated, the incoming row or column address is changed to the next higher address (+1). All modules can receive the same column address c with the ADR INC pin used to provide the c + 1 function. Some of the address lines can be grouped and...