Browse Prior Art Database

XOR and NXOR Performance Improvement

IP.com Disclosure Number: IPCOM000038746D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Blachere, JM: AUTHOR [+2]

Abstract

A possible way to implement an XOR (characterized by a low cell count), as shown in Fig. 1, presents two drawbacks: The delay to an output signal rising can be very high. The load capacitance will be charged through device 1 (or 2) and up to three P channel devices in serial corresponding to the previous stage (in this case a three-way NOR). There is one case where an output signal falling is realized with the load capacitance discharging through device 1 (or 2). The device has its gate connected to "0", thus VGS decreases more and more. The end of the transition is characterized by a high impedance. The up-down transition is not complete, and this reduced swing voltage yields a small delay penalty on the next stage (10% typical).

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XOR and NXOR Performance Improvement

A possible way to implement an XOR (characterized by a low cell count), as shown in Fig. 1, presents two drawbacks: The delay to an output signal rising can be very high. The load capacitance will be charged through

device 1 (or 2) and up to three P channel devices in

serial corresponding to the previous stage (in this

case a three-way NOR). There is one case where an output signal falling

is realized with the load capacitance discharging

through device 1 (or 2). The device has its gate

connected to "0", thus VGS decreases more and more. The

end of the transition is characterized by a high

impedance. The up-down transition is not complete, and

this reduced swing voltage yields a small delay penalty

on the next stage (10% typical).

(Image Omitted)

The proposed circuit is described in Fig. 2. The

circuit response being unchanged if inverted input

signal values are used, the circuit of Fig. 1 is driven

by the two inverters (5-6 and 7-8) which insure

decoupling from the previous stage. The complete

voltage swing during a falling delay can be done using

N channel devices (9, A) in parallel with P channel

devices (1, 2) driven by signals of opposite polarity.

This is easily done thanks to the inverters. As an example, a fan-out of two yields a 23% performance improvement whatever the transition is and 38% with regard to the worst-case situation. A possible way to implement a NXOR is shown in Fig. 3. This circuit presents two drawbacks: The output load capacitance can be discharged through device 3 (or 4) and up to four N channel

devices in serial (in this case a four-way NAND)

corresponding to the previous stage. There is one case where an output signal rising is realized with the load capacitance charging through

device 3 (or 4...