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Self-Aligned Contoured Electron Barrier for Soft Error Reduction

IP.com Disclosure Number: IPCOM000038751D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Adler, E: AUTHOR [+2]

Abstract

This article describes the formation of energy barriers by using deep buried ion implants (DBII) to avoid degradation of circuits and to reduce the soft error rate (SER). The uniqueness of this invention is the use of the polysilicon stack of the storage plate and the first polysilicon photoresist layer as a self-aligned method of profiling the DBII. Hence, no extra mask step is required to implement the invention, and no alignment tolerance noise in the detected signal results. The process to produce the structure consists of implanting (11) the wafer 12 after the first layer of polysilicon 13 is etched, with the photoresist 14 remaining in place.

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Self-Aligned Contoured Electron Barrier for Soft Error Reduction

This article describes the formation of energy barriers by using deep buried ion implants (DBII) to avoid degradation of circuits and to reduce the soft error rate (SER). The uniqueness of this invention is the use of the polysilicon stack of the storage plate and the first polysilicon photoresist layer as a self-aligned method of profiling the DBII. Hence, no extra mask step is required to implement the invention, and no alignment tolerance noise in the detected signal results. The process to produce the structure consists of implanting (11) the wafer 12 after the first layer of polysilicon 13 is etched, with the photoresist 14 remaining in place. The photoresist 14 and first polysilicon 13 reduce the range of penetration of the implant 11 into the wafer 12 only in the region where it is needed the most, just under the storage node 15. The reduction in range is proportional to the photoresist and polysilicon thicknesses and would normally be 1.5 microns for boron with a typical DBII implant energy of 2.2 MEV. In addition to improved SER reduction, an additional benefit is an increase in storage node capacitance to substrate, which will increase the cell's signal.

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