Browse Prior Art Database

Active Bus on a Wiring Wafer

IP.com Disclosure Number: IPCOM000038770D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR [+2]

Abstract

This article describes the concept of a central active bus for interconnecting VLSI chips on a common semiconductor substrate (wafer) in which, in addition to passive wiring, active elements are integrated. The VLSI chips have a high packaging density, whereas the wiring wafer may have a low packaging density but a high yield (say, 1 m technology for the VLSI chips and 5 m technology for the wiring wafer). Known IC production methods, as contrasted to conventional ceramic substrate-based technologies, permit accommodating a large number of interconnections for an equally large number of I/O pins of the VLSI chips on the wafer, which in turn permits using highly effective bus concepts. The bus arbitration logic may be centrally integrated in the wiring wafer.

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Active Bus on a Wiring Wafer

This article describes the concept of a central active bus for interconnecting VLSI chips on a common semiconductor substrate (wafer) in which, in addition to passive wiring, active elements are integrated. The VLSI chips have a high packaging density, whereas the wiring wafer may have a low packaging density but a high yield (say, 1 m technology for the VLSI chips and 5 m technology for the wiring wafer). Known IC production methods, as contrasted to conventional ceramic substrate-based technologies, permit accommodating a large number of interconnections for an equally large number of I/O pins of the VLSI chips on the wafer, which in turn permits using highly effective bus concepts. The bus arbitration logic may be centrally integrated in the wiring wafer. This allows using an active intelligent bus which is capable of performing complex control and monitoring functions for chip-to-chip communication on the wafer. Additionally, chip-to-chip communication is simplified. A logic signal typically passes an off- chip driver on the chip on which it was generated and an on-chip driver by which it is received. The receipt signal, deactivating the off-chip driver, passes a similar chain in the opposite direction. An active wiring wafer concept permits integrating off- and on-chip drivers in the substrate immediately adjacent to the respective VLSI chip, so that they directly control each other. Thus, further drivers on the individual VLSI c...