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Selectable Up/Down Counter

IP.com Disclosure Number: IPCOM000038794D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Potter, DW: AUTHOR

Abstract

A binary synchronous up/down counter is described which has a select feature providing capability to do single cycle counts of +1, 2, 3, or 4. _ Fig. 1 shows inputs In (increment) and De (decrement) to counter circuit 2, one of which is activated on each cycle. Inputs x2, x3, and x4, of which one or none is activated each cycle to counter circuit 2, provide instruction for number of steps to be taken (2, 3, or 4). No input on any of the inputs x2, x3, and x4 results in a step by one increment or decrement instruction. Clock CB input to counter circuit 2 triggers shift register latch (SRL) circuits internal to counter circuit 2 by connection to input port C1 of an SRL, one of which is shown in Fig. 2. SRLs used in counter circuit 2 are dual port units. D1 and C1 ports are used for counting functions.

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Selectable Up/Down Counter

A binary synchronous up/down counter is described which has a select feature providing capability to do single cycle counts of +1, 2, 3, or 4. _ Fig. 1 shows inputs In (increment) and De (decrement) to counter circuit 2, one of which is activated on each cycle. Inputs x2, x3, and x4, of which one or none is activated each cycle to counter circuit 2, provide instruction for number of steps to be taken (2, 3, or 4). No input on any of the inputs x2, x3, and x4 results in a step by one increment or decrement instruction. Clock CB input to counter circuit 2 triggers shift register latch (SRL) circuits internal to counter circuit 2 by connection to input port C1 of an SRL, one of which is shown in Fig.
2. SRLs used in counter circuit 2 are dual port units. D1 and C1 ports are used for counting functions. D2 and C2 ports are used to set SRLs to initial value and are not shown in Fig. 3. Fig. 3 is a five-bit counter, an example of a logic circuit diagram for counter circuit 2 of Fig. 1. In the logic circuit diagram of Fig. 3, logic elements are identified as follows: OR gate = OR

Inverter circuit = I

AND gate = A

Shift register latch = SRL (C1 and D1 ports = c and d)

(True output = T)

(Complement output = C)

Exclusive OR gate = XOR

(Image Omitted)

Inputs x2, x3, x4, In, De, and CB are indicated. Outputs T1, T2, T3, T4, and T5 not only emerge as outputs from the counter circuit but also are fed back to logic elements within the counter circuit,...