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NAND Circuit

IP.com Disclosure Number: IPCOM000038795D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+3]

Abstract

A logical "0" applied to any one or more of the inputs A, B, and C turns ON the corresponding one or more transistors T1, T2, and T3. When at least one of the transistors T1, T2, and T3 is ON, T4 will be OFF and T5 will be ON. A logical "1" will be manifested at the output of the NAND circuit. Correspondingly, a logical "1" applied to each of the inputs, A, B, and C results in a logical "0" being manifested at the output of the NAND circuit. The disclosed NAND circuit has desirable "fan-in" and "fan-out" characteristics as well as high input impedance, and low output impedance.

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NAND Circuit

A logical "0" applied to any one or more of the inputs A, B, and C turns ON the corresponding one or more transistors T1, T2, and T3. When at least one of the transistors T1, T2, and T3 is ON, T4 will be OFF and T5 will be ON. A logical "1" will be manifested at the output of the NAND circuit. Correspondingly, a logical "1" applied to each of the inputs, A, B, and C results in a logical "0" being manifested at the output of the NAND circuit. The disclosed NAND circuit has desirable "fan-in" and "fan-out" characteristics as well as high input impedance, and low output impedance.

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