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Programmable Analog-To-Digital and Digital-To-Analog Converter Circuit

IP.com Disclosure Number: IPCOM000038796D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Gokhale, A: AUTHOR

Abstract

By setting a digital/analog (DA) switch, a converter circuit becomes analog-to-digital (A-D) or digital-to-analog (D-A). Elements of the converter circuit, shown in the figure, must meet the following criteria: 1. Sample-and-hold capacitor 2 must hold a signal for a full A-D conversion cycle. 2. Comparator 4 must have accuracy of at least 10 mV for an A-D design for 8 bits and a 0-5 V range (approximately 1/2 of a least significant bit (LSB) value). 3. Control logic 6 is a combinatorial logic that performs successive approximation for A-D conversion and is attached to register 8. 4. Multiplexer 10 is two way, multiplexing bits from INBITS with output bits from register 8, and is controlled by input DA. 5. Register 12 is a clocked register. 6.

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Programmable Analog-To-Digital and Digital-To-Analog Converter Circuit

By setting a digital/analog (DA) switch, a converter circuit becomes analog-to-digital (A-D) or digital-to-analog (D-A). Elements of the converter circuit, shown in the figure, must meet the following criteria: 1. Sample-and-hold capacitor 2 must hold a signal for a full A-D conversion cycle. 2. Comparator 4 must have accuracy of at least 10 mV for an A-D design for 8 bits and a 0-5 V range (approximately 1/2 of a least significant bit (LSB) value). 3. Control logic 6 is a combinatorial logic that performs successive approximation for A-D conversion and is attached to register 8. 4. Multiplexer 10 is two way, multiplexing bits from INBITS with output bits from register 8, and is controlled by input DA. 5. Register 12 is a clocked register.

6. Digital-to-analog converter 14 may be any of several circuit configurations, e.g., a resistor ladder network. 7. Operational amplifier 16 has unity gain and is used as a buffer.

8. Switches S1, S2, S3 have less than 1/2 LSB signal degradation across each switch and a low resistance in on positions to minimize RC time constants. 9. Logical AND circuit 18 and inverter circuit 20 complete the programmable circuit. For A-D operation, input DA is set high.

This enables S2, disables S3 and sets multiplexer 10 inputs from register 8. Sampling clock C1 provides a frequency for sampling analog input AI. Clock C1 also presets register 12 to a binary representation...