Browse Prior Art Database

Delay Margin Testing Circuit for CMOS Circuitry

IP.com Disclosure Number: IPCOM000038804D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR [+2]

Abstract

An automated high volume delay margin testing means for critical delay paths in CMOS designs is shown utilizing DC control voltage techniques. Currently a double-inverter circuit configuration, shown in Fig. 1, is used to isolate manually directed orbital probes when making critical delay path measurements on CMOS designs. If automatic testing is required, a probe card connection at node A is needed, but this introduces an unacceptable capacitive load which distorts test results. To increase or decrease delays without changing the rise and fall characteristics of the output pulse, node A is overridden with an AC pulse. This precludes doing margin testing on an automated high volume tester. By using a basic CMOS inverter, shown in Fig. 2, in series with a p-channel device (Fig. 3) or a n-channel device (Fig.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 60% of the total text.

Page 1 of 2

Delay Margin Testing Circuit for CMOS Circuitry

An automated high volume delay margin testing means for critical delay paths in CMOS designs is shown utilizing DC control voltage techniques. Currently a double-inverter circuit configuration, shown in Fig. 1, is used to isolate manually directed orbital probes when making critical delay path measurements on CMOS designs. If automatic testing is required, a probe card connection at node A is needed, but this introduces an unacceptable capacitive load which distorts test results. To increase or decrease delays without changing the rise and fall characteristics of the output pulse, node A is overridden with an AC pulse. This precludes doing margin testing on an automated high volume tester. By using a basic CMOS inverter, shown in Fig. 2, in series with a p-channel device (Fig. 3) or a n-channel device (Fig. 4), both of which have DC control means, a double- inverter testing structure is formed, allowing high volume automated delay margin testing. Fig. 3 shows a series p-channel device (TC) with a high resistance low current device (TD) used to keep the gate of TC biased to TD's ground voltage and a test pad. The test pad is normally floating or at ground, and when overridden with a DC voltage the current through TC is changed. Fig. 4 shows the same concept implemented with the opposite types of devices. TE is a series n-channel device with a high resistance low current device (TF) used to keep the gate of TE normall...