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Low Cost Method for Determining the Minumum Cycle Time of High Speed RAM Chips

IP.com Disclosure Number: IPCOM000038837D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Chappell, TI: AUTHOR [+2]

Abstract

This publication describes a method that allows the minimum cycle time of high speed RAMs to be determined accurately with only a low cost frequency counter. As the performance of memory chips has improved, their testing at full operating speed has become so difficult that existing VLSI testers cannot be used. Instead, only the access time is measured directly using the VLSI tester. Their minimim cycle time must be determined separately from a special, stand-alone test jig or estimated from the design of the chip. This makes it uneconomical to sort chips according to minimum cycle time for applications in systems where the minimum cycle time is an important parameter.

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Low Cost Method for Determining the Minumum Cycle Time of High Speed RAM Chips

This publication describes a method that allows the minimum cycle time of high speed RAMs to be determined accurately with only a low cost frequency counter. As the performance of memory chips has improved, their testing at full operating speed has become so difficult that existing VLSI testers cannot be used. Instead, only the access time is measured directly using the VLSI tester. Their minimim cycle time must be determined separately from a special, stand-alone test jig or estimated from the design of the chip. This makes it uneconomical to sort chips according to minimum cycle time for applications in systems where the minimum cycle time is an important parameter. To overcome this problem, a solution has been provided to measure the frequency of oscillation of the memory chip when it is connected in a way to make it cycle at its minimum cycle time. This greatly simplifies the measurement and allows a low cost frequency counter to be employed. The minimum cycle time is given by 1/frequency measured with the counter. The circuit used to make the memory chip oscillate at its minimum cycle time is shown in the figure. The example shown is for a 64K RAM chip activated by chip select NOT (CSN) falling (see, for example, 1986 ISSCC Digest, pp. 206-7). To prepare the memory chip for measurement, the VLSI tester is used to load the RAM chip with a "1" at any address having the least significant bit of the X address (XLSB) set to "0" and a "0" at any address with XLSB="1". The XLSB line is connected to Data Out. Data Out is connected to CSN through a variable delay and gates U1 and U2 . TTL circuits U1 and U...