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Multiple Pattern Recognition Using Finite STATE Automation

IP.com Disclosure Number: IPCOM000038859D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Barker, KJ: AUTHOR

Abstract

This article describes a pattern recognition device in which single bits of an incoming data stream are combined with the device's current STATE outputs in order to generate the devices Next State. The State Transition Table is stored in a random-access memory (RAM), allowing ease of change. When the incoming data stream is such that the State Transition ends up at the MATCH STATE, an indication is given. The multiple pattern recognition device may be viewed as a Finite State Machine that can be built from off-the-shelf components with the State Transition Table stored in RAM. The device steps through the State Transition Table (on a realtime basis) based on the incoming data. External output lines can be activated to cause storage of incoming data, the triggering of other devices, and the synchronization of external devices.

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Multiple Pattern Recognition Using Finite STATE Automation

This article describes a pattern recognition device in which single bits of an incoming data stream are combined with the device's current STATE outputs in order to generate the devices Next State. The State Transition Table is stored in a random-access memory (RAM), allowing ease of change. When the incoming data stream is such that the State Transition ends up at the MATCH STATE, an indication is given. The multiple pattern recognition device may be viewed as a Finite State Machine that can be built from off-the-shelf components with the State Transition Table stored in RAM. The device steps through the State Transition Table (on a realtime basis) based on the incoming data. External output lines can be activated to cause storage of incoming data, the triggering of other devices, and the synchronization of external devices. These lines can be activated at any State of the Transition Table. The incoming bit stream can be searched for a number of different patterns simultaneously. The number of patterns is dependent on the length of each pattern and the size of the RAM containing the State Transition Table. As shown in the accompanying figure, the pattern recognition device includes a pattern storage device (RAM) in which the user-defined patterns are stored. A communications bus 10 interconnects the pattern-stored device to an N-bit address register. The output from the N-bit address register is fed over communication bus 12 to the storage devce address space. Stated another way, the output from...