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Staggered B Clock in LSSD Testing

IP.com Disclosure Number: IPCOM000038878D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Kupeski, ML: AUTHOR [+3]

Abstract

Disclosed is a technique for improving the testing of chips by reducing the noise generated during a level sensitive scan design (LSSD) test. Referring to Fig. 1, in LSSD designs, all sequential elements are implemented as shift register latches (SRLs) 10 mounted on a chip 12. Each of the SRLs 10 contains two actual latches L1 and L2. Typically, system data enters the first latch L1 under the control of a system clock C. Data is then transferred to the second latch L2 under the control of a shift B Clock. System data is transmitted by a selected SRL 10 through its associated second latch L2. In such designs, internal logic circuits 12, 13 and 14 and high-current switching off-chip drivers 16 are coupled to the second latch L2 of the SRLs 10.

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Staggered B Clock in LSSD Testing

Disclosed is a technique for improving the testing of chips by reducing the noise generated during a level sensitive scan design (LSSD) test. Referring to Fig. 1, in LSSD designs, all sequential elements are implemented as shift register latches (SRLs) 10 mounted on a chip 12. Each of the SRLs 10 contains two actual latches L1 and L2. Typically, system data enters the first latch L1 under the control of a system clock C. Data is then transferred to the second latch L2 under the control of a shift B Clock. System data is transmitted by a selected SRL 10 through its associated second latch L2. In such designs, internal logic circuits 12, 13 and 14 and high-current switching off-chip drivers 16 are coupled to the second latch L2 of the SRLs 10.

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The greatest electrical activity on the chip occurs when the B Clock is enabled. The enabling of the B Clock may cause the internal logic circuit 12, 13 and 14 to switch, developing a concentrated delta in current. This concentrated delta in current can and does disturb the latch contents as noise is propagated back into the chip 12 from glitches on signal and power supply inputs. Moreover, this disturbance can change the binary state of a latch which may cause a subsequent test failure. As shown in Fig. 2, the electrical switching activity can be minimized by distributing the switching activity initiated by turning on the B Clock. The reduction in switching activity also redu...