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Boundary Logic Multi-Chip Module Testing

IP.com Disclosure Number: IPCOM000038882D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

LeBlanc, JJ: AUTHOR [+2]

Abstract

Shift register latches (SRLs) which appear on a periphery of a chip mounted on a multi-chip module (MCM) are utilized to test chip-to-chip interconnections. Referring to Figs. 1 and 2, a plurality of chips 10 are mounted on a MCM 12. Each of the chips 10 includes an internal logic circuit 14 and a plurality of SRLs 16 appearing along the periphery of a chip. Additionally, each of the chips 10 is designed so that the internal logic circuit 14 can be electronically isolated from the SRLs 16. As shown in Fig. 2, the SRLs 16 can be coupled together in a scan string in order to facilitate the testing thereof using level sensitive scan (Image Omitted) design (LSSD) techniques. Moreover, each of the chips 10 is tested at the wafer level in order to detect failures within each chip.

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Boundary Logic Multi-Chip Module Testing

Shift register latches (SRLs) which appear on a periphery of a chip mounted on a multi-chip module (MCM) are utilized to test chip-to-chip interconnections. Referring to Figs. 1 and 2, a plurality of chips 10 are mounted on a MCM 12. Each of the chips 10 includes an internal logic circuit 14 and a plurality of SRLs 16 appearing along the periphery of a chip. Additionally, each of the chips 10 is designed so that the internal logic circuit 14 can be electronically isolated from the SRLs 16. As shown in Fig. 2, the SRLs 16 can be coupled together in a scan string in order to facilitate the testing thereof using level sensitive scan

(Image Omitted)

design (LSSD) techniques. Moreover, each of the chips 10 is tested at the wafer level in order to detect failures within each chip. Thereafter, the chips 10 are mounted on the MCM 12 and coupled together by chip-to-chip interconnections 18, as shown in Fig. 3. Referring to Fig. 3, the chips 10 also include a plurality of drivers 20 (one shown) and a plurality of receivers 22 (one shown). The drivers 20 and the receivers 22, in conjunction with the interconnections 18, facilitate the flow of data between the chips 10 mounted on the MCM 12. As noted above, each of the chips 10 has been tested at the wafer level using LSSD techniques. The SRLs 16 are tested independently of the logic circuit 14. In order to test the SRLs 16, (1) the SRLs are coupled into a scan string and (2) data, ap...