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New Fast Page Mode Design in CMOS Dynamic Ram

IP.com Disclosure Number: IPCOM000038884D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Lu, NC: AUTHOR [+4]

Abstract

This article describes a new fast page mode design for CMOS DRAM (dynamic random-access memory), which has much faster column access time and shorter cycle time in contrast to conventional page mode design. Fig. 1 shows the timing diagrams of conventional page mode and the new fast page mode. In conventional page mode design, CAS low activates the address buffer and then decoder which selects the column switch to allow data transfer from bit-lines to an input/output sense amplifier. When CAS is high, the column circuit is reset (precharged) and prepared ready for the next active cycle. The column cycle time includes the time for address buffer, column decoder, I/O sense amplifier, data output buffer, data valid, and column precharge.

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New Fast Page Mode Design in CMOS Dynamic Ram

This article describes a new fast page mode design for CMOS DRAM (dynamic random-access memory), which has much faster column access time and shorter cycle time in contrast to conventional page mode design. Fig. 1 shows the timing diagrams of conventional page mode and the new fast page mode. In conventional page mode design, CAS low activates the address buffer and then decoder which selects the column switch to allow data transfer from bit-lines to an input/output sense amplifier. When CAS is high, the column circuit is reset (precharged) and prepared ready for the next active cycle. The column cycle time includes the time for address buffer, column decoder, I/O sense amplifier, data output buffer, data valid, and column precharge. In the new fast page mode, both address buffer and column decoder use CMOS static circuits which do not need precharge and so the time to activate the address buffer and column decoder is hidden in the column precharge period. As a result, the column cycle time includes only the time for I/O sense amplifier, data output buffer, data valid, and column precharge, and is shorter than the conventional page mode cycle time. The circuits to achieve this fast page mode are shown in Fig. 2. Both address buffer and column decoder use CMOS static circuits. When

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the row circuits are activated and CAS is high, the clock /CAB is high to allow the input address to set the decoder and th...