Browse Prior Art Database

Next-Sequential Prefetching Using a Branch History Table

IP.com Disclosure Number: IPCOM000038893D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

The present invention uses a Branch History Table (BHT) to perform Next Sequential Instruction (NSI) prefetching. The use of a BHT to perform NSI prefetching has several advantages over standard approaches to NSI prefetching. These advantages derive from the fact that it is the branches within the line that determine whether or not NSI is correct. A correct BHT can serve as a basis for this prediction, and the prediction is updateable as the branching activity within the line becomes manifest. It is also clear that lines of instructions are enterable at multiple points and the correctness of NSI can be sensitive to the entry point. A BHT activated NSI algorithm would clearly be entry-point sensitive, but the action of the BHT must not be interfered with to any major extent as NSI is added as part of the BHT activity.

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Next-Sequential Prefetching Using a Branch History Table

The present invention uses a Branch History Table (BHT) to perform Next Sequential Instruction (NSI) prefetching. The use of a BHT to perform NSI prefetching has several advantages over standard approaches to NSI prefetching. These advantages derive from the fact that it is the branches within the line that determine whether or not NSI is correct. A correct BHT can serve as a basis for this prediction, and the prediction is updateable as the branching activity within the line becomes manifest. It is also clear that lines of instructions are enterable at multiple points and the correctness of NSI can be sensitive to the entry point. A BHT activated NSI algorithm would clearly be entry-point sensitive, but the action of the BHT must not be interfered with to any major extent as NSI is added as part of the BHT activity. In the present invention, each BHT entry is augmented with a single bit, X, which is set at the time the entry is made in BHT. The X is set to zero if NSI is indicated; X is set to 1, otherwise. For example, X=0 if the branch entry is either a forward branch whose target is internal to the current line or whose target is in the next sequential line. The BHT must further be organized so that all the branches within a cache line are read out when an access is made to the BHT. Due to its branch prediction requirements, such a BHT will identify all branches currently recognized within the line that...