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Revising Next Sequential Confirmations Based on Last MRU Action

IP.com Disclosure Number: IPCOM000038898D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+5]

Abstract

This invention provides an improved mechanism for detecting sequential program behavior and utilizes this information to increase the accuracy of confirmed sequential prefetching. In high end machines the performance opportunity for next sequential (NS) prefetching is limited when large caches are involved. The prefetching benefit may be 25% of the finite cache effect (FCE), which in turn may only be of the order of 25% of the overall performance. Such systems with a relatively small FCE have unused bus capacity which allows for greater prefetch inaccuracy in order to achieve higher coverage. At the other extreme, there are machines which have much larger FCE and a larger benefit from prefetching, this must be achieved with higher accuracy, even if that accuracy is achieved at the expense of coverage.

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Revising Next Sequential Confirmations Based on Last MRU Action

This invention provides an improved mechanism for detecting sequential program behavior and utilizes this information to increase the accuracy of confirmed sequential prefetching. In high end machines the performance opportunity for next sequential (NS) prefetching is limited when large caches are involved. The prefetching benefit may be 25% of the finite cache effect (FCE), which in turn may only be of the order of 25% of the overall performance. Such systems with a relatively small FCE have unused bus capacity which allows for greater prefetch inaccuracy in order to achieve higher coverage. At the other extreme, there are machines which have much larger FCE and a larger benefit from prefetching, this must be achieved with higher accuracy, even if that accuracy is achieved at the expense of coverage. Increasing accuracy at the expense of coverage requires that the confirmation not be based merely on the detection of sequentiality on a miss from the cache and the persistence of correct prefetching but on other events as well.

In this disclosure, the sequentiality within a cache is monitored together with detection of sequentiality on a miss from the cache and the persistence of correct prefetching. This is accomplished as follows: On every MRU change to line X, (say) when line X+1 is in the cache but not MRU in its congruence class, the confirmation bit is turned off and X+1 is treated as a prefetch...