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Fault-Tolerant Battery Monitor and Charger

IP.com Disclosure Number: IPCOM000038901D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Kress, JE: AUTHOR [+3]

Abstract

A technique is described whereby a microprocessor-controlled switching circuit provides a means of detecting defective batteries, as used to retain data in memory arrays, allowing the defective batteries to be replaced without disturbing the accuracy of the non-volatile memory. In addition, the circuit provides a means of charging a battery and to indicate when a battery is to be replaced. Since a battery must be present in order to properly maintain data as written into computer memory data banks should primary power be lost, the circuit described herein provides assurance that five basic functions exist: 1. The battery is maintained at full charge while primary power is present. 2. The battery state is periodically tested at zero charge current, and a defective battery is detected. 3.

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Fault-Tolerant Battery Monitor and Charger

A technique is described whereby a microprocessor-controlled switching circuit provides a means of detecting defective batteries, as used to retain data in memory arrays, allowing the defective batteries to be replaced without disturbing the accuracy of the non-volatile memory. In addition, the circuit provides a means of charging a battery and to indicate when a battery is to be replaced. Since a battery must be present in order to properly maintain data as written into computer memory data banks should primary power be lost, the circuit described herein provides assurance that five basic functions exist: 1. The battery is maintained at full charge while primary power is present. 2. The battery state is periodically tested at zero charge current, and a defective battery is detected. 3. The load is supplied by the charger during the testing of the battery. 4. The battery will automatically switch on-line to power the memory units when power is lost, so as to insure

the integrity of the data in the memory. 5. The data integrity in the memory must be maintained during replacement of the battery. Transistors Q1 and Q2, as shown in the figure, are used to direct the charger current to either the battery or the memory unit, depending upon the command state of microprocessor 10. When the output of microprocessor 10 is high, Q2 is off, enabling transistor Q1 to provide a constant current to charge battery 11. Q1 also supplies t...