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Implementation, Simulation, and Verification of Hardware Design Using a Single Truth Table

IP.com Disclosure Number: IPCOM000038904D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Brooks, N: AUTHOR [+7]

Abstract

A simplified method of designing and simulating hardware is accomplished using only one truth table. The conventional method of logic design occurs in three distinct phases, each phase requiring unique data to complete. First, a truth table is generated corresponding to the desired logic function, and the hardware is implemented from this table. Next, an additional set of data is generated to use in the system level simulation of the design. Finally, another set of data is used to verify that the logic is implemented properly. A method in which one table is used for all three phases is implemented as follows. (Image Omitted) Fig. 1 shows the truth table that describes the logic function desired. A logic reduction program then takes the table and reduces it to minimal form (Fig. 2).

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Implementation, Simulation, and Verification of Hardware Design Using a Single Truth Table

A simplified method of designing and simulating hardware is accomplished using only one truth table. The conventional method of logic design occurs in three distinct phases, each phase requiring unique data to complete. First, a truth table is generated corresponding to the desired logic function, and the hardware is implemented from this table. Next, an additional set of data is generated to use in the system level simulation of the design. Finally, another set of data is used to verify that the logic is implemented properly. A method in which one table is used for all three phases is implemented as follows.

(Image Omitted)

Fig. 1 shows the truth table that describes the logic function desired. A logic reduction program then takes the table and reduces it to minimal form (Fig. 2). This form contains only those states necessary to achieve the desired output. This minimal form is used for logic implementation. Fig. 3 is an example in which this logic is implemented from the minimal table in Fig. 2, where the function to set output W is described. All terms in a row are ANDed together. All ANDed terms are then ORed together to produce the function. Common terms that appear throughout the table are grouped together. This allows different functions to be built using as many common blocks as possible.

(Image Omitted)

The minimal form of the table is also used for system simulati...