Browse Prior Art Database

Power-On Reset Circuit

IP.com Disclosure Number: IPCOM000038920D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Graves, SB: AUTHOR [+2]

Abstract

An improved monitor/protection circuit, i.e., a power-on reset circuit (POR), (Fig. 1) is described which not only monitors electronic logic supply voltage and the operation of a pair of microprocessors but simultaneously controls and protects high current circuits in associated input/output devices, such as a printer card. It disables the high (Image Omitted) current electronics in the event of either a voltage drop or a processor software reset. In either case, the processor electronics are in an unknown state which could cause damage. POR also generates power on reset signals for the respective processors. For purposes of this article, it will be assumed that POR disables a motor control driver and a print head driver in the event of a supply voltage failure or a processor failure.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 50% of the total text.

Page 1 of 3

Power-On Reset Circuit

An improved monitor/protection circuit, i.e., a power-on reset circuit (POR), (Fig. 1) is described which not only monitors electronic logic supply voltage and the operation of a pair of microprocessors but simultaneously controls and protects high current circuits in associated input/output devices, such as a printer card.

It disables the high

(Image Omitted)

current electronics in the event of either a voltage drop or a processor software reset. In either case, the processor electronics are in an unknown state which could cause damage. POR also generates power on reset signals for the respective processors. For purposes of this article, it will be assumed that POR disables a motor control driver and a print head driver in the event of a supply voltage failure or a processor failure. POR monitors the following conditions: 1. Power-up sequence

2. Processor keep-alive fail "high" condition

3. Processor keep-alive fail "low" condition

4. Power-down sequence

(Image Omitted)

The power-up and power-down sequence monitoring uses the same circuitry. Its function is to sense whether the 5-volt supply (logic supply) is above or below 4.5 volts. If the supply is above 4.5 volts, it is assumed that the processors are in control and the proper drive signals are applied to the high current drivers (motor, print head, etc.). If the supply is below 4.5 volts, it disables the motor and print head drivers, and a reset signal is supplied to the processors by A4. Specifically, comparator A1 compares the reference voltage level at node 2 (which is set at 4.5 volts by the high positive supply 1 (+36 V), resistor R17 and zener diode D34) with the nominal +5-volt supply level coupled to input 3. If the input 3 is above 4.5 volts, the output 4 of A1 permits a positive bias to be applied to the drivers at lines 5, 6 via resistors R24, R25 and diodes 8 and 9. If the input 3 is below 4.5 volts, output 4 of A1 via diode 7 pulls the bias to ground potential at 5, 6 to turn "off" the drivers irrespective of the state of their input control signals. Ground potential at node 15 also causes A4 to produce a positive output signal to reset the processors via line 13. The second function of POR is to sense when the processors are being reset or are out of control. The reset signals are produced by control circuit 10 and are cyclic in nature. That is, a reset pulse is generated for 1.6 MS (high level), then goes low for 1.6 MS. This continues until the processor starts functioning. Comparator A2 senses this pulse train (Fig. 2A) via diodes 11, 12, line 13, buffer A3, line 14 and diode D36 and controls the driver bias points 5 and 6

1

Page 2 of 3

accordingly. The diode D36 allows capacitor C28 to charge quickly while resistor R20 discharges C28 slowly. This holds the bias points down during the low state of the pulse train. This integration process is necessary since driving the bias points at a 3.2 MS pulse rate would not cause sufficient curre...