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Selectable BUS Byte Order Circuit

IP.com Disclosure Number: IPCOM000038923D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

St. Clair, JC: AUTHOR

Abstract

The figure illustrates a circuit that allows a feature card to be attached to two styles of system buses: those that define data bits 0-7 as the most significant bits, and those that define data bits 8-15 as the most significant bits. Some systems define data bits 0-7 to be the Least Significant Byte (LSB) while bits 8-15 form the Most Significant Byte (MSB). Other systems define bits 0-7 to be the MSB and bits 8-15 to be the LSB. When attaching a feature card to either of these two styles of systems, the circuit described below allows the byte ordering to be correct for both system styles.

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Selectable BUS Byte Order Circuit

The figure illustrates a circuit that allows a feature card to be attached to two styles of system buses: those that define data bits 0-7 as the most significant bits, and those that define data bits 8-15 as the most significant bits. Some systems define data bits 0-7 to be the Least Significant Byte (LSB) while bits 8-15 form the Most Significant Byte (MSB). Other systems define bits 0-7 to be the MSB and bits 8-15 to be the LSB. When attaching a feature card to either of these two styles of systems, the circuit described below allows the byte ordering to be correct for both system styles.

Without this circuit, the microprocessor attached to the local bus of the feature card would frequently need to execute code to interchange (or swap) the two bytes that compose the 16-bit words when the card was attached to the system that uses the "wrong" byte ordering. The speed penalty inherent in executing this extra swap code is unacceptable in the intended application of this feature card. The circuit, shown in the figure, operates as follows: At power-on time, flip-flop 3 is RESET so that its

output "Q" is low. This disables NAND gate 4 and

enables NAND gate 5 so that the BUFFER ENABLE signal

can be used to enable buffers 2A and 2B while buffers

1A and 1B cannot be enabled. With flip-flop 3 thus

reset, the local microprocessor's MSB is associated

with SYSTEM BUS bits 8-15 and its LSB is associated

with SYSTEM BUS bits 0-7. By writing a...