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High-Performance Microcode Command Architecture

IP.com Disclosure Number: IPCOM000038930D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Freeman, WA: AUTHOR [+2]

Abstract

A method is described to maximize the efficiency of the process of issuing commands to a processor. The design of an attachment adapter that contains a processor presents a number of design trade-offs concerning the ease of interfacing and adapter performance. This invention provides a means by which the majority of the adapter commands can be initiated as a result of a single I/O write operation. This technique removes the requirement that the system processor and the adapter processor be synchronized during the command initiation process. The addition of a processor to a device attachment adapter permits this adapter to provide an extremely flexible solution to a variety of device attachment problems.

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High-Performance Microcode Command Architecture

A method is described to maximize the efficiency of the process of issuing commands to a processor. The design of an attachment adapter that contains a processor presents a number of design trade-offs concerning the ease of interfacing and adapter performance. This invention provides a means by which the majority of the adapter commands can be initiated as a result of a single I/O write operation. This technique removes the requirement that the system processor and the adapter processor be synchronized during the command initiation process. The addition of a processor to a device attachment adapter permits this adapter to provide an extremely flexible solution to a variety of device attachment problems. In the IBM RT PC Multi-Protocol Communications Adapter, the adapter processor permits this adapter to provide a powerful, high performance solution to the problem of attachment to a variety of data communications devices and networks. Inherent with this variety is a problem of the complexity of the command interface that must be supported. In accordance with the new method, a `three- tiered' command architecture and a single 8-bit command path is employed. The use of a single 8-bit command path permits initiation of adapter processor commands to be accomplished via a single I/O writer operation. This 8-bit command field must then be defined in such a way as to encompass all of the required adapter functions. In the c...