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Dual-Phase Power-On Reset Module

IP.com Disclosure Number: IPCOM000038931D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

De Filippi, RJ: AUTHOR

Abstract

Disclosed is a circuit which generates a positive reset pulse and a negative reset pulse when power is initially applied to the circuit. Referring to Fig. 1, a standard transistor-transistor logic module 10 is modified by adding two resistor-capacitor circuits to inputs thereof. The values of the resistors and capacitors in circuits R1C1 and R2C2, having time constants t1 and t2, respectively, are chosen such that t2 equals 100t1 . Referring to Figs. 1 and 2, at time t0, a positive voltage signal is applied simultaneously to circuits R1C1 and R2C2. Capacitors C1 and C2 are charged through resistors R1 and R2, respectively, to a threshold voltage level. Capacitor C1, which attains the threshold voltage level at time t1 as shown in Fig.

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Dual-Phase Power-On Reset Module

Disclosed is a circuit which generates a positive reset pulse and a negative reset pulse when power is initially applied to the circuit. Referring to Fig. 1, a standard transistor-transistor logic module 10 is modified by adding two resistor- capacitor circuits to inputs thereof. The values of the resistors and capacitors in circuits R1C1 and R2C2, having time constants t1 and t2, respectively, are chosen such that t2 equals 100t1 . Referring to Figs. 1 and 2, at time t0, a positive voltage signal is applied simultaneously to circuits R1C1 and R2C2. Capacitors C1 and C2 are charged through resistors R1 and R2, respectively, to a threshold voltage level. Capacitor C1, which attains the threshold voltage level at time t1 as shown in Fig. 2(A), facilitates the generation of a low-level signal on output line 12 of NAND gate 14, as shown in Fig. 2(D). This low-level signal is also fed to an inverter 16 and appears as a high-level signal on output line 18, as shown in Fig. 2(E). Thereafter, capacitor C2 attains the threshold voltage level at time t2, as shown in Fig. 2(B). An inverter 20, which is coupled to the R2C2 circuit, feeds a low-level signal to an input of NAND gate 14, as shown in Fig. 2(C). The signal appearing on output line 12 changes to a high-

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level signal while its complement appears on output line 18. Thus, negative and positive reset pulses are generated on output lines 12 and 18, respectively, as shown...