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Redundancy Using Platinum-Silicon Fuses

IP.com Disclosure Number: IPCOM000038940D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Fitzpatrick, DA: AUTHOR [+2]

Abstract

It has been proposed that PtSi films used in bipolar semiconductor devices be utilized as fuses in place of metal fuses or other techniques. It will make it possible to implement redundancy without process change or multiple part numbers. The proposal makes it possible to selectively blow the fuses to deactivate defective word or bit lines and also encode any desired address on the redundant line. In a conventional redundancy scheme with, for example, 10-bit output (Fig. 1), (each output may have 8-bit lines 2 and a total of 2048 memory cells. One or more defective cells make an output bad. If one of the outputs 3 is bad, it is eliminated through personalized module wiring 4 and the chip is usable. If two or more outputs are bad, the chip is rejected.

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Redundancy Using Platinum-Silicon Fuses

It has been proposed that PtSi films used in bipolar semiconductor devices be utilized as fuses in place of metal fuses or other techniques. It will make it possible to implement redundancy without process change or multiple part numbers. The proposal makes it possible to selectively blow the fuses to deactivate defective word or bit lines and also encode any desired address on the redundant line. In a conventional redundancy scheme with, for example, 10- bit output (Fig. 1), (each output may have 8-bit lines 2 and a total of 2048 memory cells. One or more defective cells make an output bad. If one of the outputs 3 is bad, it is eliminated through personalized module wiring 4 and the chip is usable. If two or more outputs are bad, the chip is rejected. This means that even if only two cells are bad but they happen to be in two different outputs, the chip is rejected. In the proposed redundancy scheme there are only 9 outputs (Fig.

(Image Omitted)

2) as against 10 in the earlier design. Fixed module wiring 6 is used since there is no need for personalized module wiring; the part number is reduced from 10 to one. Each of the outputs has its own redundant line 7, making for a total number of 81 bit lines as compared with 80 in the original redundancy scheme of Fig. 1. The address decoder of the redundant line is activated and encoded with the desired address by blowing fuses during electrical test of the wafer. The decoder of the faulty line is permanently deactivated by blowing a fuse during the same electrical test. There are several ways of deactivating selected word or bit lines and encoding desired addresses in redundant lines or cells during the electrical test. One such scheme is outlined in Fig. 3, wherein one extra emitter is added to the multi-emitter input device Q1 of the address decoder. The emitter is normally held at a positive potential by the voltage divider resistors R1 and R3 which are tied to suitable positive and negative potentials. The pad P2 is held at a negative potential but is left floating during wafer testing so that the extra emitter does not inhibit the decoder during fuse blowing. When the tester finds a bad cell, the address is frozen. Node B at the output of the selected decoder is positive, while the same node in all of the other decoders is nega

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