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Overlap of Cache-To-Cache Transfer With Outpage Operation Within a Dual-Processor Machine

IP.com Disclosure Number: IPCOM000038946D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Jackson, EW: AUTHOR

Abstract

In a dual-processor machine, cache-to-cache transfer operations are the means in which modified cache pages are moved from the cache of one processor to the cache of the other. In the general case a storage microword is issued which gets a cache miss. The cache directory least recently used (LRU) algorithm points to an invalid, or unmodified, cache slot, and an inpage operation is started. A search in the other processor's cache directory finds the desired data with a modified status. The inpage operation is then terminated, and a cache-to-cache operation is executed instead. No penalty of extra machine cycles is incurred.

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Overlap of Cache-To-Cache Transfer With Outpage Operation Within a Dual-Processor Machine

In a dual-processor machine, cache-to-cache transfer operations are the means in which modified cache pages are moved from the cache of one processor to the cache of the other. In the general case a storage microword is issued which gets a cache miss. The cache directory least recently used (LRU) algorithm points to an invalid, or unmodified, cache slot, and an inpage operation is started. A search in the other processor's cache directory finds the desired data with a modified status. The inpage operation is then terminated, and a cache-to-cache operation is executed instead. No penalty of extra machine cycles is incurred. An exception case exists which increases, by an average of sixteen machine cycles, the time taken to complete a cache-to-cache transfer operation when the cache slot pointed to by the cache directory's LRU algorithm is modified. This exception case is as follows. 1. A storage microword is issued that gets a cache miss. The cache directory LRU algorithm points to a

"modified" cache slot, and an outpage operation is

started. 2. A search in the other processor's cache directory

finds the desired data with a status of "modified." 3. The outpage operation is allowed to continue, but the cache directory status of the data brought into the

cache is set to "invalid" rather than "valid," as would

normally be the case. The potential cache-to-cache

operation is terminated. 4. Upon completion of the "cache load" portion of the outpage operation, the storage micro word is reissued.

It again gets a cache miss, but now traps out due to

the BSM (Basic Storage Module) controls being "busy"

with the "unload swap buffer" portion of the outpage

operation. 5. Upon completion of the outpage operation, the

storage microword is again reissued, and now the

operation will proceed as per the general case

description. The entire operation will take 57 machine cycles on the average, 41 for the outpage and 16 for the subsequent cache-to-cache transfer. The outpage operation is necessary to "open up" a cache slot for...