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Programmable Power Planes for Multichip Modules

IP.com Disclosure Number: IPCOM000038948D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Krouse, DR: AUTHOR

Abstract

Packages for high I/O integrated circuit chips typically use multilayer ceramic substrates for chip carriers. These substrates contain signal planes for interconnecting chips in multichip packages and for connecting the chip I/O's with the package I/O's. They also contain continuous power planes for distributing power to each chip. Because certain electronic packages are designed to carry chips of different technology families on the same substrate, each chip may have different power requirements. A method of providing different power requirements is to divide the continuous power planes into segments, one segment for each required voltage for each chip. The required power is then connected to each segment and distributed to each corresponding chip. The method works as follows.

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Programmable Power Planes for Multichip Modules

Packages for high I/O integrated circuit chips typically use multilayer ceramic substrates for chip carriers. These substrates contain signal planes for interconnecting chips in multichip packages and for connecting the chip I/O's with the package I/O's. They also contain continuous power planes for distributing power to each chip. Because certain electronic packages are designed to carry chips of different technology families on the same substrate, each chip may have different power requirements. A method of providing different power requirements is to divide the continuous power planes into segments, one segment for each required voltage for each chip. The required power is then connected to each segment and distributed to each corresponding chip. The method works as follows. Each power plane in a multilayer ceramic substrate is divided into a number of areas equivalent to the number of chips provided for on the substrate. These areas, the size of the chip sites, serve as individual power elements for each chip. Each element connects through vias to a set of pins and supplies the required voltage to the chip. Thus, a power plane may support more than one voltage. To increase the coupling capacitance of the elements, the elements may be bussed together on the personalization layers. The voltage required by each chip could be selected and programmed during personalization wiring. In this manner, a single substrate w...