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Fast DRAM Sensing With Sense Amplifiers Synchronous to Bitline Delays

IP.com Disclosure Number: IPCOM000038952D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Chin, D: AUTHOR [+3]

Abstract

A dynamic random-access memory (DRAM) sensing circuit is described for successively tracking bitline delays and activating sense amplifiers. In a conventional DRAM design, wordline delay is simulated by a sample wordline (SWL) whose physical structure is identical to an actual wordline (WL). After receiving the worst-case signal at the farthest bitline from a second metal patch in a block, an intermediate clock (dS) is generated, as shown in Fig. 1. Then two subsequent clocks (dS and dSDP) are generated to supply GND and VDD to all sense amplifiers through large latching NMOS and PMOS devices, respectively. In other words, a sense amplifier is not latched until the slowest bitline signal is developed and three clocks are fully delivered.

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Fast DRAM Sensing With Sense Amplifiers Synchronous to Bitline Delays

A dynamic random-access memory (DRAM) sensing circuit is described for successively tracking bitline delays and activating sense amplifiers. In a conventional DRAM design, wordline delay is simulated by a sample wordline (SWL) whose physical structure is identical to an actual wordline (WL). After receiving the worst-case signal at the farthest bitline from a second metal patch in a block, an intermediate clock (dS) is generated, as shown in Fig. 1. Then two subsequent clocks (dS and dSDP) are generated to supply GND and VDD to all sense amplifiers through large latching NMOS and PMOS devices, respectively. In other words, a sense amplifier is not latched until the slowest bitline signal is developed and three clocks are fully delivered. The total time necessary from wordline set-up to latch sensing is the sum of delay times of the slowest bitline signal development and three-clock generation/propagation. Furthermore, since all sense amplifiers are latched at the same time, dI/dt, the most serious noise source in a high density/performance DRAM, is very large at the moment.

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This publication describes a novel sample wordline and sensing scheme that not only simulates the actual wordline delay, but activates sense amplifiers at different times according to individual bitline delay. As shown in Fig. 2, this new SWL scheme consists of three sample wordlines: one for slow sensing with a PMOS array identical to an actual wordline (noted as SSWL), and the other two for fast sensing with larger PMOS and NMOS devices that supply VDD and GND to a sense amplifier (SWL and SWL, respectively). Since the delay in the slow s...