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Hardware Recirculation Sorter

IP.com Disclosure Number: IPCOM000038958D
Original Publication Date: 1987-Mar-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Ashley, DJ: AUTHOR

Abstract

A recirculation sorter performs an ascending or descending order on bytes of binary data. A three-dimensional array, linked by binary magnitude (Fig. 1) comparators, determines the processing order. This hardware sorter improves the performance of the operating systems' sorting capabilities. The bytes of binary data are sequentially pushed into the sorter with a bit concatenated to the most significant bit (MSB) position for an indication of the input/output phase of operation to a bit steering network (Fig. 2). (Image Omitted) The binary magnitude comparators compare side by side xy registers, at each level of the 3-D array simultaneously. Control logic will transfer the register with the minimum/maximum binary magnitude data into the vacated register below.

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Hardware Recirculation Sorter

A recirculation sorter performs an ascending or descending order on bytes of binary data. A three-dimensional array, linked by binary magnitude (Fig. 1) comparators, determines the processing order. This hardware sorter improves the performance of the operating systems' sorting capabilities. The bytes of binary data are sequentially pushed into the sorter with a bit concatenated to the most significant bit (MSB) position for an indication of the input/output phase of operation to a bit steering network (Fig. 2).

(Image Omitted)

The binary magnitude comparators compare side by side xy registers, at each level of the 3-D array simultaneously. Control logic will transfer the register with the minimum/maximum binary magnitude data into the vacated register below. When the Xn or Yn data from the bottom cell confronts the I/O steering network (which directs this data through an I/O bit complementing function), the data is recirculated into the vacated top cell (Fig. 3). Additional clocks continue the recirculation until the steering network receives a flush command from data that is represented as sorted because the I/O bit = set (Fig. 4).

(Image Omitted)

Once the flush command has been set, N clocks (N = Vector length) will push the sorted data through the steering network which then gates the data onto the system databus. The sorter primarly consists of edge-triggered data hold latches whose outputs feed a binary magnitude comparator (Fi...