Browse Prior Art Database

Clock-Free Latched Sense Amplifier for Bipolar RAM

IP.com Disclosure Number: IPCOM000038973D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+3]

Abstract

The present disclosure describes a sense amplifier which includes a latch for the data out in order to take place in a clocked bipolar random-access memory (RAM) because it is directly set/reset by means of the bit line current. In a typical application, the circuit may be used in a 36K RAM, physically organized as a 144 x 256-cell matrix, and logically as a 2K x 18. It is a clocked RAM; this means that in stand-by mode, each cell is deselected and 18 pairs of bit line current (IBL) sources are ON among 144. These 18 pairs of IBL sources which are ON correspond to the previous bit address which has been stored in a special "address latch".

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Clock-Free Latched Sense Amplifier for Bipolar RAM

The present disclosure describes a sense amplifier which includes a latch for the data out in order to take place in a clocked bipolar random-access memory (RAM) because it is directly set/reset by means of the bit line current. In a typical application, the circuit may be used in a 36K RAM, physically organized as a 144 x 256-cell matrix, and logically as a 2K x 18. It is a clocked RAM; this means that in stand-by mode, each cell is deselected and 18 pairs of bit line current (IBL) sources are ON among 144. These 18 pairs of IBL sources which are ON correspond to the previous bit address which has been stored in a special "address latch". Then, even if this bit address is erroneously damaged, the IBL's are kept constant, and can be used in the data-latched sense amplifier, to store the content of one cell (1 data bit of the last selected word). The read operation will be better understood with reference to the figure. In the stand-by mode, the 256 words are deselected, and the two sense transistors, which the base connected to SAR (Sense Amplifier Reference), are ON together and they drive the current IBL, which is used in the data latch. This latch needs two internal references: a 3 VBE = 2.4 V and VR 2.1 = 2.1 V. If we assume that the content of the previous selected cell was such that the data latch transistors are in the following state: Stand-by mode ---> TSAL, TSAR ON T1L, T3R, T2R ON

T2L, T3L, T1R OFF a 1...