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Optimal Sequential Testing Scheme for VLSI Circuits

IP.com Disclosure Number: IPCOM000038975D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 26K

Publishing Venue

IBM

Related People

Lee, YH: AUTHOR [+2]

Abstract

This invention provides an efficient testing scheme that applies the optimal testing period to test VLSI circuits and simultaneously estimates production yield. As the density of VLSI circuits increases, the testing pattern applied to the VLSI circuits can no longer test for all possible defects. Therefore, minimum testing needs must be determined. In general, there are two kinds of costs associated with the testing process: the cost of testing itself and the cost of passing as good an imperfect circuit. An optimal testing strategy should trade off both costs and determine an adequate test length (in terms of testing period or number of test patterns).

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Optimal Sequential Testing Scheme for VLSI Circuits

This invention provides an efficient testing scheme that applies the optimal testing period to test VLSI circuits and simultaneously estimates production yield. As the density of VLSI circuits increases, the testing pattern applied to the VLSI circuits can no longer test for all possible defects. Therefore, minimum testing needs must be determined. In general, there are two kinds of costs associated with the testing process: the cost of testing itself and the cost of passing as good an imperfect circuit. An optimal testing strategy should trade off both costs and determine an adequate test length (in terms of testing period or number of test patterns). Once the production yield and the coverage function of a testing pattern are known, the optimal testing period or test length that minimizes the total cost of testing can be determined. The production yield, however, of every run may not be known a priori and should be estimated using test results. Thus, test results should be fed back to estimate the production yield. The estimated yield, then, is used to determine the optimal testing period for testing the subsequent circuits and will affect all subsequent test results. Sequential Testing Scheme The flow diagram of sequential testing and estimation is illustrated in the figure. The proposed scheme assumes that the probability of having a defect at a circuit under test is described by a sequence of probabilistic measures wi, where the index i is used to indicate the sequence of tested circuits. The prior density function of wi before the testing of the i-th circuit is denoted by ei(w). The means and variance of wi are denoted by - i and si, respectively. The coverage function of the testing process is described by a distribution function Fs(t) which, in turn, is with the density function fs(t)...