Browse Prior Art Database

Address LATCH With Intermediate Reference

IP.com Disclosure Number: IPCOM000038980D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Akrout, C: AUTHOR [+3]

Abstract

The present disclosure describes a latched receiver with improved AC performances based on the use of a third transistor connected to an intermediate reference. (Image Omitted) The latter leads to a faster data acquisition, and the latch current source does not need to be switched any more. Principle (Fig. 1) When an address is stored in the address latch (ADD LATCH), CLK is pulled up and CLK is pulled down. Because the latch content is isolated from the data bus, it can be used to provide the reset data. Then, data has to be present on the bus at least during the clock pulse and the address signal skew is avoided. A special intermediate reference for the address latch improves the minimum clock pulse requirement. Description of the invention (Fig. 2) Both the receiver and the latch are ECL (emitter coupled logic) circuits.

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Address LATCH With Intermediate Reference

The present disclosure describes a latched receiver with improved AC performances based on the use of a third transistor connected to an intermediate reference.

(Image Omitted)

The latter leads to a faster data acquisition, and the latch current source does not need to be switched any more. Principle (Fig.
1) When an address is stored in the address latch (ADD LATCH), CLK is pulled up and CLK is pulled down. Because the latch content is isolated from the data bus, it can be used to provide the reset data. Then, data has to be present on the bus at least during the clock pulse and the address signal skew is avoided. A special intermediate reference for the address latch improves the minimum clock pulse requirement. Description of the invention (Fig. 2) Both the receiver and the latch are ECL (emitter coupled logic) circuits. There is an intermediate reference in the latch to improve the switching delay.

If data is present at the input receiver (ADD), (TR1 or TR2 ON, according to the address), and CLK is high (--- is low), the data is stored in the ADD latch. Next, CLK is set at a low level (i.e., CLK is high), and the data bus is available (the new address can be prepared). The base voltage of TRef is connected to the intermediate reference (VIR). Its value is chosen to be equal to the mean voltage of the ADD latch internal nets. The switching cycle of that latch is explained with reference to Fig. 3, which shows the base...