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CTS Inverter Circuit

IP.com Disclosure Number: IPCOM000038990D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR

Abstract

This article describes a novel inverter circuit which is configurated from a Complementary Transistor Switch (CTS) memory cell. The new circuit resembles the write operation of a CTS cell, hence providing a more direct AC characterization means to evaluate the cell's write performance [*]. It can also be used as a delay circuit for on-chip timing generation. Fig. 1 shows the circuit of this CTS inverter. It is formed from an unclamped CTS cell with writing and driving peripheral devices added. Transistors T1 and T2 are writing elements, whereas T3 and T4 are driving and isolation devices between stages. The CTS cell is powered by voltage supply Vp through resistor Rp; either one of them could be (Image Omitted) changed to adjust the SCR's operating current level. Typical cell current is set between 1 mA - 30 mA.

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CTS Inverter Circuit

This article describes a novel inverter circuit which is configurated from a Complementary Transistor Switch (CTS) memory cell. The new circuit resembles the write operation of a CTS cell, hence providing a more direct AC characterization means to evaluate the cell's write performance [*]. It can also be used as a delay circuit for on-chip timing generation. Fig. 1 shows the circuit of this CTS inverter. It is formed from an unclamped CTS cell with writing and driving peripheral devices added. Transistors T1 and T2 are writing elements, whereas T3 and T4 are driving and isolation devices between stages. The CTS cell is powered by voltage supply Vp through resistor Rp; either one of them could be

(Image Omitted)

changed to adjust the SCR's operating current level.

Typical cell current is set between 1 mA - 30 mA. The cell is switched (or written) by driving transient current from T1 or T2 into one side of the bit Schotty barrier diodes (SL or SR) while the other side is being held off. The magnitude of this write current is controlled by an up-level clamp line (UC), which is designed to track with the cell devices to temperature and power supply variations. The write time of the cell (hence, delay generated) is a function of the amount of write current applied. The CTS inverter has two inputs and two output lines which are of opposite phases. Either an even or odd number of stages can be concatenated to form a circulating loop or a delay chain...