Browse Prior Art Database

Two-Party Bus Arbitration for Floating-Point Operation

IP.com Disclosure Number: IPCOM000039013D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Cocanougher, D: AUTHOR [+2]

Abstract

A technique is described whereby a tightly coupled bus arbitration logic concept is used in high utilization floating-point computer operation, so as to provide fast transferring of operands to multiple and divide sub-units of a two-chip floating-point unit (FPU). The arbitration scheme is applicable to two-party bus floating- point operations, where one party requires 100% usage and control of the bus and will release the bus to requesters on all occasions, yet can force the requester to keep the bus when the owner requires the result for a longer period of time. The arbitration bus is used between the two chips (upper and lower) of the FPU. It is a data bus used for transferring operands to the multiple and divide sub-units on the lower FPU and for transferring the results back to the upper FPU.

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Two-Party Bus Arbitration for Floating-Point Operation

A technique is described whereby a tightly coupled bus arbitration logic concept is used in high utilization floating-point computer operation, so as to provide fast transferring of operands to multiple and divide sub-units of a two-chip floating- point unit (FPU). The arbitration scheme is applicable to two-party bus floating- point operations, where one party requires 100% usage and control of the bus and will release the bus to requesters on all occasions, yet can force the requester to keep the bus when the owner requires the result for a longer period of time. The arbitration bus is used between the two chips (upper and lower) of the FPU. It is a data bus used for transferring operands to the multiple and divide sub-units on the lower FPU and for transferring the results back to the upper FPU. Result transfers have priority of the bus over operand transfers, enabling the lower FPU to have bus priority. The upper FPU owns the bus unless the lower FPU requests it. The lower FPU will signal that it requires the results on the cycle prior to the transfer. The upper FPU monitors the arbitration line and will never enable the bus during the transfer cycle. This averts any bus conflict, enabling the upper FPU to re-do any operation for a transfer during the next cycle.

(Image Omitted)

The timing chart in Fig. 1 shows examples of how the request and send lines are activated to control the FPU bus. When a request...