Browse Prior Art Database

Programmable Dot Clock for Video Adapter

IP.com Disclosure Number: IPCOM000039045D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Landers, JD: AUTHOR

Abstract

A programmable clock provides a wide range of frequencies for a video adapter, thereby permitting the adapter to be used with different types of video monitors. The dot clock in a video adapter is the fundamental timing signal that drives all the logic in the adapter. Typical adapters are designed with fixed frequency oscillators. Some adapters are designed with circuitry that can select, under program control, a frequency that is a binary division of a fixed frequency oscillator. Limitations of this technique are the extremely high frequencies involved which give rise to EMC problems, require high speed high current logic devices, and still do not give a wide selection of frequencies. An alternative to this approach is shown in the drawing.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 58% of the total text.

Page 1 of 2

Programmable Dot Clock for Video Adapter

A programmable clock provides a wide range of frequencies for a video adapter, thereby permitting the adapter to be used with different types of video monitors. The dot clock in a video adapter is the fundamental timing signal that drives all the logic in the adapter. Typical adapters are designed with fixed frequency oscillators. Some adapters are designed with circuitry that can select, under program control, a frequency that is a binary division of a fixed frequency oscillator. Limitations of this technique are the extremely high frequencies involved which give rise to EMC problems, require high speed high current logic devices, and still do not give a wide selection of frequencies. An alternative to this approach is shown in the drawing. This circuit is composed of a fixed frequency oscillator 1, divide-by-N- and-M programmable counters 2 and 3, and a phase-locked loop (PLL) 4. PLL 4 is composed of a phase comparator circuit 5, a low-pass filter 6, and a voltage controlled oscillator (VCO). PLL 4 locks the output of the VCO to the input signal f1. The output of the phase comparator is a voltage proportional to the instantaneous phase difference of the input signals f1 and f2. The output of the phase comparator (which is a mixer) contains both the sum and difference frequencies of the input signals. The low-pass filter removes the sum frequency and applies the difference frequency to the VCO. This is a closed-loop, posi...