Browse Prior Art Database

One-Step Etchback

IP.com Disclosure Number: IPCOM000039065D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Brooks, GA: AUTHOR [+4]

Abstract

Disclosed is an ion milling method to expose studs in semiconductor devices which is much simpler than conventional processing and which guarantees that the studs will be planarized and exposed. (Image Omitted) In conventional multilevel metallization (MLM) processing, a complex number of steps and etchbacks are required to prepare the studs for the interconnection metal. These required multiple steps add to the expense of production and often leave studs unopened. Additionally, they may leave a step at a stud which makes it susceptible to failure. The conventional reactive ion etch (RIE) process begins at a metallurgy level 1 (Fig. 1A) with studs 2 ready for further processing. Planar SiO2 3 (Fig. 1B) is deposited, and photoresist 4 applied.

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One-Step Etchback

Disclosed is an ion milling method to expose studs in semiconductor devices which is much simpler than conventional processing and which guarantees that the studs will be planarized and exposed.

(Image Omitted)

In conventional multilevel metallization (MLM) processing, a complex number of steps and etchbacks are required to prepare the studs for the interconnection metal. These required multiple steps add to the expense of production and often leave studs unopened. Additionally, they may leave a step at a stud which makes it susceptible to failure. The conventional reactive ion etch (RIE) process begins at a metallurgy level 1 (Fig. 1A) with studs 2 ready for further processing. Planar SiO2 3 (Fig. 1B) is deposited, and photoresist 4 applied. The device is baked and then an RIE etchback is followed by an O2 plasma ashing (Fig. 1C). An insulating nitride Si3N4 layer 5 (Fig. 1D) is deposited, another layer of resist applied, and a mask exposed for the desired structure. A second RIE of the vias followed by a plasma ashing completes the structure, as indicated. The proposed method, illustrated in sequential steps in Figs. 2A-2D, begins with the metallurgy 1 and studs 2, as before. The insulating Si3N4 layer 5 followed by a SiO2 layer 3 are then deposited. Planarizing polyimide or novalak 6 is next applied, and the film is hardened in a baking operation. Ion milling is performed to achieve the final planarized structure of Fig. 2D. The advantages of...