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LSSD Testable Derived B Clock Design

IP.com Disclosure Number: IPCOM000039066D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Hanna, SD: AUTHOR [+2]

Abstract

A circuit design process is described which eliminates the need to bring derived B clocks in an LSSD design to an I/O pin to guarantee that all clocking faults in the B clock structure are testable. As compared to known LSI-structured designs, this can free one or more I/O pins for other purposes. The circuit implementation, as shown, makes the derived B clock testable by using it (properly gated by Clock Isolation pin(s)) to clock an L2* SRL system clock port or an L1 system port. Since the system clocks for L2* SRLs and L1 latches are testable, the B clock becomes testable without the use of a valuable I/O pin. This configuration does not need to be separate from the system design.

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LSSD Testable Derived B Clock Design

A circuit design process is described which eliminates the need to bring derived B clocks in an LSSD design to an I/O pin to guarantee that all clocking faults in the B clock structure are testable. As compared to known LSI-structured designs, this can free one or more I/O pins for other purposes. The circuit implementation, as shown, makes the derived B clock testable by using it (properly gated by Clock Isolation pin(s)) to clock an L2* SRL system clock port or an L1 system port. Since the system clocks for L2* SRLs and L1 latches are testable, the B clock becomes testable without the use of a valuable I/O pin. This configuration does not need to be separate from the system design. As used in this description and in the drawing, "LSSD" means Level Sensitive Scan Design, "SRL" means shift register latch, "PI BS" means primary input, combination B and system clock, "COMB LOGIC" means combinational logic, and "CLK ISO" means clock isolation control which allows use of the clock primary input BS as a shift clock in scan mode and then as a normal system clock in system operation.

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