Browse Prior Art Database

First Data Change Detection

IP.com Disclosure Number: IPCOM000039075D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Lewis, DO: AUTHOR [+2]

Abstract

This invention detects and signals the first attempt to change a main store page and prevents changes to the page until the unaltered page can be processed. This is accomplished through changes to the central processing unit (CPU) hardware, horizontal microcode (HMC) and by adding an additional indicator to each primary directory entry and lookaside buffer entry. On the IBM System/38, internal-microprogram instructions use virtual addresses which must be translated to resolved main store addresses before the addressed page can be accessed. A primary directory (PD) maps virtual to resolved addresses. A lookaside buffer (LB) is a partial copy of the PD containing portions of recently used PD entries. The CPU hardware performs translations using the LB.

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First Data Change Detection

This invention detects and signals the first attempt to change a main store page and prevents changes to the page until the unaltered page can be processed. This is accomplished through changes to the central processing unit (CPU) hardware, horizontal microcode (HMC) and by adding an additional indicator to each primary directory entry and lookaside buffer entry. On the IBM System/38, internal-microprogram instructions use virtual addresses which must be translated to resolved main store addresses before the addressed page can be accessed. A primary directory (PD) maps virtual to resolved addresses. A lookaside buffer (LB) is a partial copy of the PD containing portions of recently used PD entries. The CPU hardware performs translations using the LB. If the required PD entry (PDE) is not in the LB, the hardware signals HMC which then loads the PDE into the LB and repeats the translation. If a page is to be altered, HMC indicates this to the CPU hardware via a set change bit (SCB) command at the time of the translation. The SCB causes the hardware to set an indicator in the LB (LB change bit) which HMC later uses to set a corresponding indicator in the PD (PD change bit). The requirement for a translation with SCB prior to altering a page is the key to first change detection. An extra bit (PD exception bit) is added to each PDE. VMC sets the bit to enable first change detection for a page. Similarly, an extra bit (LB trap bit) is added to each LB entry. HMC sets the bit to enable the hardware change detection trap for a page when the PD change bit is off (indicating that the page has not been altered) and the PD exception bit is on (see Table
1). When HMC requests a translate with SCB, the hardware examines the LB trap bit (see table 2). If the bit is on, the translate is aborted, the LB change bit is not set, and the hardware traps (branches) HMC to a special routine. HMC then nullifies the instruction (as is done for a page fault) and signals an exceptio...