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Algorithm for Fast Address Testing of Memory Components and Memory Boards

IP.com Disclosure Number: IPCOM000039079D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 4 page(s) / 56K

Publishing Venue

IBM

Related People

Farrell, AE: AUTHOR

Abstract

The algorithm tests memory components and memory boards for internal addressing problems and particularly for data integrity at memory locations which have a distance of 1 from a base address. By its using just two data values and a minimum number of locations, errors due to addressing can be detected and isolated to memory components or memory boards. This same algorithm is employed in testing memory boards containing parity bits. Diagnostic routines have existed for testing memory boards and for isolating single memory devices which have internal data accessing failures, and this algorithm complements that testing by isolating memory addressing problems. Data integrity routines employ multiple data patterns and access every memory location.

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Algorithm for Fast Address Testing of Memory Components and Memory Boards

The algorithm tests memory components and memory boards for internal addressing problems and particularly for data integrity at memory locations which have a distance of 1 from a base address. By its using just two data values and a minimum number of locations, errors due to addressing can be detected and isolated to memory components or memory boards. This same algorithm is employed in testing memory boards containing parity bits. Diagnostic routines have existed for testing memory boards and for isolating single memory devices which have internal data accessing failures, and this algorithm complements that testing by isolating memory addressing problems. Data integrity routines employ multiple data patterns and access every memory location. These routines may also verify addressing integrity through multiple patterns and by testing every memory location. This addressing verification is minimized by observing that if one address bit is in error, either on the memory board or internal to the memory device itself, there will be two unique addresses which point to one memory location (see Fig. 1). By holding all other address bits constant and changing one bit at a time, a test can be made to check for this occurrence. This algorithm, therefore, accesses only those locations which differ by exactly one address bit from a base address, i.e., there is a distance of 1 between the addresses. This minimization, while identifying address errors, is not considered a replacement for testing cell-to-cell isolation in the memory device itself but is presented as a means to isolate errors due strictly to addressing.

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Using location '0' as the base, 64Kx1 (64K by 1) and 256Kx1 Dynamic Random-Access Memories (DRAMs) require only 8 and 9 other locations, respectively. (Other memory devices can also be tested with this algorithm using a number of locations corresponding to the number of address inputs each has.)

This algorithm uses two data patterns: a data word of all zeros, and a data word of all ones. The same routine may be used to check parity devices, assuming the data devices are error-free, by also using only two data patterns. These two patterns must differ in parity, i.e., one data pattern to generate odd parity and another to generate even parity. The ability to test parity devices assumes a method to monitor parity status exists without causing system disruption. This article illustrates a 2-byte memory word, therefore using data patterns of '0000' and 'FFFF' hex, for testing the data devices. The parity devices use data patterns of '0000' and '0101' hex. (Note: Parity checking is performed on each byte, so the parity for each byte changes although the parity for the word remains the same.) The algorithm used is detailed below. The algorithm is detailed for testing the data and parity devices separately. DATA DEVICES:

1

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1. Initially a d...