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Process-Controlled Bit Line Restore

IP.com Disclosure Number: IPCOM000039082D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+3]

Abstract

A circuit array is additionally provided with one switchable restore device for each bit line to avoid high currents that occur during best process bit line restoring. The switchable restore device is driven by a split driver signal generated from a process-independent reference signal. At the end of a read/write cycle, the bit line is restored. As restoring must be completed before the start of a fresh read/write cycle, the worst-case, i.e., the slowest, process has to be considered for sizing the restore devices. Under best-case, i.e., fastest, process conditions, there is a high current flow, reducing the restoring time. This may lead to interference effects, such as a drop in potential, electromigration, noise, etc. The described array, shown in Fig.

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Process-Controlled Bit Line Restore

A circuit array is additionally provided with one switchable restore device for each bit line to avoid high currents that occur during best process bit line restoring. The switchable restore device is driven by a split driver signal generated from a process-independent reference signal. At the end of a read/write cycle, the bit line is restored. As restoring must be completed before the start of a fresh read/write cycle, the worst-case, i.e., the slowest, process has to be considered for sizing the restore devices. Under best-case, i.e., fastest, process conditions, there is a high current flow, reducing the restoring time. This may lead to interference effects, such as a drop in potential, electromigration, noise, etc. The described array, shown in Fig. 1, has two restore FETs T1 and T2 for each bit line, which are gated by signals RBL1 and RBL2. The control of the additional FET T2 is shown in Fig. 2 by way of a time/ signal curve. The array is accessed by changing the array select signal AS from high to low. The trailing edge of signal AS triggers the split driver signal SD and forces reference signal REF to high with a certain delay. Reference signal REF is controlled such that it occurs at the same time as set sense amplifier signal SSA, assuming nominal conditions. As a process-independent signal, reference signal REF, compared with set sense amplifier signal SSA, occurs at the fixed time Tnom with only little delay varia...