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High Noise Immunity CMOS Driver

IP.com Disclosure Number: IPCOM000039084D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Fischer, W: AUTHOR [+3]

Abstract

A driver circuit is proposed with an adjustable hysteresis in its transfer characteristics, allowing an individual setting of the switching threshold for positive and negative input transitions. The output pulse is shaped by a feedback trigger circuit providing steep transitions independently of the slope of the input pulse. A conventional CMOS driver, consisting of two cascaded inverter stages, normally requires a compromise between high noise immunity, which should be about equal for both levels, and good switching characteristics. An improved circuit, as illustrated in the figure, consists of a flip-flop feedback circuit with transistors T1 to T4, which is steered by an input inverter stage with transistors T5 and T6.

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High Noise Immunity CMOS Driver

A driver circuit is proposed with an adjustable hysteresis in its transfer characteristics, allowing an individual setting of the switching threshold for positive and negative input transitions. The output pulse is shaped by a feedback trigger circuit providing steep transitions independently of the slope of the input pulse. A conventional CMOS driver, consisting of two cascaded inverter stages, normally requires a compromise between high noise immunity, which should be about equal for both levels, and good switching characteristics. An improved circuit, as illustrated in the figure, consists of a flip-flop feedback circuit with transistors T1 to T4, which is steered by an input inverter stage with transistors T5 and T6. The switching thresholds are adjustable by the size ratio of T6 to T1 and T5 for the down level and T5 to T6 and T2 for the up level. The output transition is controlled by the feedback circuit, and is therefore always fast and nearly independent of the input slope. The transistor ratios may be adjusted such that the two thresholds overlap, causing a hysteresis in the transfer characteristics. Two additional transistors T7 and T8 provide increased design freedom for the individual setting of the switching thresholds and the delay as well as for the transitional current flow and the relationship between the layout and the current amplification. In the quiescent state, either T7 or T8 is conducting. As the input volt...