Browse Prior Art Database

Memory Map Protection Circuit

IP.com Disclosure Number: IPCOM000039104D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 4 page(s) / 54K

Publishing Venue

IBM

Related People

Piazza, WJ: AUTHOR

Abstract

This article describes protection circuitry for data processing systems which prevents a storage facility or input/output (I/O) ports from being altered except by authorized users. It is desirable to protect storage or I/O ports in a microprocessor-based system, for example, from being changed in an unauthorized manner. Many systems have multiple users and it is important to prevent access of users to selected areas of the system. For instance, a particular piece of software may be maintaining a table in storage. A casual or accidental change in the table may cause the program to crash or produce other undesirable results.

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Memory Map Protection Circuit

This article describes protection circuitry for data processing systems which prevents a storage facility or input/output (I/O) ports from being altered except by authorized users. It is desirable to protect storage or I/O ports in a microprocessor-based system, for example, from being changed in an unauthorized manner. Many systems have multiple users and it is important to prevent access of users to selected areas of the system. For instance, a particular piece of software may be maintaining a table in storage. A casual or accidental change in the table may cause the program to crash or produce other undesirable results. The protection circuitry described herein allows a particular range of memory addresses to be set up as a "window" characterized as a memory map into which authorized software must fit before it will be allowed to modify a particular area that needs protection. Fig. 1 is a generalized system diagram of the protection feature applied to a microprocessor system including a protected device. Most microprocessors, such as microprocessor 1, allow external circuitry, such as state decoder 2, to decode their "state". It is possible to detect the moment that the microprocessor is performing its "instruction fetch," evidenced by a signal on line 3, and to store the address from which the instruction is being fetched by way of a latch circuit 4. The address, derived from bus 6, is then decoded by decoder 7 and used in making a decision as to whether or not other devices in the system should be enabled.

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The circuit shown in Fig. 1 can be designed so that latch 4 always captures the address from which an instruction is fetched and decoder 7 produces an active "enable" signal via line 9 to AND gate 10 only if this address is in the range X'0000' to X'OFFF' or some other range of addresses which is appropriate for the application. A program running at location X'0500' would thus be allowed to alter the protected device 11 which may be a storage facility, I/O or other device. A program running at X'7000', however, would not be allowed to change the protected device. The program at X'7000' is forced to call the routine at X'0500' to alter the device, and this gives control over how it is changed. Fig. 2 illustrates the application of the protection feature to a programmable read-only memory (PROM). The storage map protection cir

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cuit described can be used to implement "Execute Only" storage, i.e., storage which can be neither written to nor read from but which contains machine instructions that will execute properly. A piece of proprietary software may be burned into a read-only memory and become

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a part of a machine to be made available to the public. A memory map of the storage, designated 15, includes User RAM and Proprietary RAM and PROM. If left unprotected, a user can write a program and place it in User RAM which would read the PROM, possibly for...